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asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 1 - general description the AK4537 targeted at pda and other low - power, small size applications. it features a 16 - bit stereo codec with a built - in microphone - amplifier, headphone - amplifier and speaker - amplifier. input circuits inclu de a microphone - amplifier and an alc (auto level control) circuit. the AK4537 is available in a 52 - qfn, utilizing less board space than competitive offerings. features 1. resolution : 16bits 2. recording function stereo mic input stereo line input 1 st mi c amplifier : +20db or 0db 2 nd amplifier with alc +27.5db ~ - 8db, 0.5db step (mic input) +12db ~ - 23.5db, 0.5db step (line input) adc performance : s/(n+d) : 79db, dr, s/n : 83db (mic input) s/(n+d) : 88db, dr, s/n : 91db (line input) 3. playback function digital de - emphasis filter (tc=50/15 m s, fs=32khz, 44.1khz, 48khz) digital volume (0db ~ - 127db, 0.5db step, mute) stereo headphone - amp - s/(n+d) : 70db, s/n : 90db - output power : 15mw@16 w (hvdd=3.3v) - click noise free at power on/off mono speak er - amp with alc - s/(n+d) : 64db@150mw, s/n : 90db - btl output - output power : 300mw@8 w , thd+n=10% (hvdd=3.3v) mono and stereo beep inputs mono line output - differential output - performance : s/(n+d) : 89db, s/n : 95db stereo line output - perfor mance : s/(n+d) : 88db, s/n : 92db 4. power management 5. master clock (1) pll mode frequencies : 11.2896mhz, 12mhz and 12.288mhz input level : cmos (2) external clock mode frequencies : 2.048mhz ~ 12.288mhz 6. output master clock frequencies : 32fs/64fs/128fs/256fs 7. sampling rate : (1) pll mode 8khz, 11.025khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz (2) external clock mode 8khz ~ 48khz 8. control mode: 4 - wire serial / i 2 c bus 9. master/slave mode 16 - bit d s stereo codec with m ic/hp/spk - amp AK4537
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 2 - 10. audio interface format : msb first, 2?s compliment adc : i 2 s, 16 bit msb justified dac : i 2 s, 16bit msb justified, 16bit lsb justified 11. ta = - 10 ~ 70 c 12. power supply: 2.4v ~ 3.6v (typ. 3.3v) 13. power supply current avdd+dvdd : 19ma pvdd : 1.2ma hvdd (hp - amp=on, spk - amp=off) : 4ma hvdd (hp - amp=off, spk - amp= on) : 7ma 12. package : 52pin qfn (ak4534 pin compatible) n block diagram alc1 (ipga) avdd avss micoutl lin1 lrck bick sdto sdti pdn dsp and up dvdd dvss hvdd hvss vcom mutet alc2 mout- hpl pmhpl hp-amp hpr pmhpr hp-amp control register interface audio pmspk spk- amp spp spn i2c csn/cad1 cclk/scl cdti/sda cdto pmmo cad0 mout+ xti/mcki xto mcko vcoc pvdd pvss mix mix mix mpe mic power supply ext /micr int /micl mic-amp 0db or 20db mpi mic power supply m/s hpf adc pmdac datt smute dac min mout2 mix pll pmpll pmxtl beepl beepr pmbps beepm pmbpm lin2 alc1 (ipga) rin1 lout rout rin2 mic-amp 0db or 20db micoutr pmmicr att pmlo att att pmmicl pmmicr or pmipgr pmmicl or pmipgl pmadl or pmadr mix mix pmmix mix mix mix pmmicl figure 1 . block diagram
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 3 - n ordering guide AK4537vn - 10 ~ +70 c 52pin qfn (0.4mm pitch) akd4537 evaluation board for AK4537 n pin layout ext /micr rin1 52 51 1 50 49 48 47 46 45 44 43 42 39 38 37 36 35 34 33 32 31 30 29 24 23 22 21 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 AK4537vn top view mpe mpi int /micl vcom avss avdd pvdd pvss cclk/scl dvdd dvss xto xti/mcki m/s spp spn hvdd hvss hpr hpl beepl beepr beepm lin2 rin2 mout+ mout- lout mout2 12 vcoc 25 28 nc 41 min csn/cad1 pdn cdti/sda cdto i2c sdti sdto lrck bick mcko nc 13 26 27 40 nc rout lin1 cad0 mutet micoutl micoutr
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 4 - n comparison with ak4534 1. function function ak4534 AK4537 line input no yes (stereo) mic input mono stereo ipga mono stereo stereo line output no yes spk - amp gain select no yes mout g ain select no yes path from ipga lch to analog output no yes 2. pin pin# ak4534 AK4537 1 micout micoutl 2 tst1 micoutr 3 ext ext/micr 6 int int/micl 42 tst2 rout 43 tst3 lout 46 tst4 rin2 47 tst5 lin2 51 ain lin1 52 nc rin1 3. register addr contents 00h pmipgl (ipga lch power control ) is added. pmlo (stereo line output power control ) is added. 01h spkg (spk - amp output power select) is added. 02h mogn (mout gain select) is added. micm (ipga lch ? mout) is added 03h pslo (stereo line output power save mode select) is added. micl (ipga lch ? lout/rout, hp - amp, spk - amp) is added. 05h hplm, hprm (hp - amp mono output select) is deleted. hpm (hp - amp mono output select) is added. 07h ipgac (ipga control) is added. 0eh attm (ipga lch ? mout att s elect) is added. atts2 - 0 (ipga lch ? lout/rout, hp - amp, spk - amp att select) is added. 0fh ipgar6 - 0 (rch ipga control) is added. 10h pmadr (adc rch power control) is added. pmmicr (mic - amp rch power control) is added. pmipgr (ipga rch power control) is ad ded. inl (ipga lch input select) is added. inr (ipga rch input select) is added.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 5 - pin/function no. pin name i/o function 1 micoutl o mic - amp lch output pin 2 micoutr o mic - amp rch output pin ext i external microphone input pin ( mon o input) (pmmi cr bit = ? 0 ? ) 3 micr i stereo microphone rch input pin (pmmicr bit = ? 1 ? ) 4 mpe o mic power supply pin for external microphone / stereo microphone rch 5 mpi o mic power supply pin for internal microphone / stereo microphone lch ext i internal micropho ne input pin ( mon o input) (pmmicl bit = ? 0 ? ) 6 micr i stereo microphone lch input pin (pmmicl bit = ? 1 ? ) 7 vcom o common voltage output pin, 0.45 x avdd bias voltage of adc inputs and dac outputs. 8 avss - analog ground pin 9 avdd - analog power supply pin 10 pvdd - pll power supply pin 11 pvss - pll ground pin 12 vcoc o output pin for loop filter of pll circuit this pin should be connected to pvss with one resistor and capacitor in series. 13 nc - no connect. this pin should be left floating. 14 c ad0 i chip address 0 select pin 15 pdn i power - down mode pin ? h ? : power up, ? l ? : power down reset and initializes the control register. csn i chip select pin (i2c = ? l ? ) 16 cad1 i chip address 1 select pin (i2c = ? h ? ) cclk i control data clock pin (i2c = ? l ? ) 17 scl i control data clock pin (i2c = ? h ? ) cdti i control data input pin (i2c = ? l ? ) 18 sda i/o control data input pin (i2c = ? h ? ) 19 cdto o control data output pin (i2c = ? l ? ) 20 i2c i control mode select pin ? h ? : i 2 c bus, ? l ? : 4 - wire ser ial 21 sdti i audio serial data input pin 22 sdto o audio serial data output pin 23 lrck i /o input / output channel clock pin 24 bick i/o audio serial data clock pin 25 mcko o master clock output pin 26 nc - no connect. this pin should be left floati ng.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 6 - no. pin name i/o function 27 nc - no connect. this pin should be left floating. 28 dvdd - digital power supply pin 29 dvss - digital ground pin 30 xto o x ? tal output pin xti i x ? tal input pin 31 mcki i external master clock input pin 32 m/s i master / slave mode pin ? h ? : master mode, ? l ? : slave mode 33 spp o speaker amp positive output pin 34 spn o speaker amp negative output pin 35 hvdd - headphone amp power supply pin 36 hvss - headphone amp ground pin 37 hpr o rch headphone amp output pin 38 hpl o lch headphone amp output pin 39 mutet o mute time constant control pin connected to hvss pin with a capacitor for mute time constant. 40 min i alc input pin 41 mout2 o analog mixing output pin 42 rout o rch stereo line output pin 43 lout o lch stereo line output pin 44 mout - o mono line negative output pin 45 mout+ o mono line positive output pin 46 rin2 i rch analog input 2 pin (line input) 47 lin2 i lch analog input 2 pin (line input) 48 beepm i mono beep signal input p in 49 beepr i rch stereo beep signal input pin 50 beepl i lch stereo beep signal input pin 51 lin1 i rch analog input 1 pin (mic input) 52 rin1 i lch analog input 1 pin (mic input) note: all input pins except analog input pins (int, ext, lin1, rin1, min, beepm, beepl, beepr, lin2 and rin2) should not be left floating.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 7 - a bsolute maximum ratings (avss , dvss, pvss, hvss= 0v ; note 1 ) parameter symbol min max units power supplies: analog avdd - 0.3 4.6 v digit al dvdd - 0.3 4.6 v pll pvdd - 0.3 4.6 v headphone - amp / speaker - amp hvdd - 0.3 4.6 v |avss ? pvss| ( note 2 ) d gnd1 - 0.3 v |avss ? dvss| ( note 2 ) d gnd2 - 0.3 v |avss ? h vss| ( note 2 ) d gnd3 - 0.3 v input current, any pin except supplies iin - 10 ma analog input voltage vina - 0.3 avdd+0.3 v digital input voltage vind - 0.3 dvdd+0.3 v ambient temperature (powered applied) ta - 10 70 c storage temperature tstg - 65 150 c note 1 . all voltages with respect to ground . note 2 . avss, dvss, pvss and hvss must be connected to the same analog ground plane . warning : operation at or beyond the se limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions ( avss, dvss, pvss , hvss =0v ; note 1 ) parameter symbol min typ max uni ts power supplies analog avdd 2.4 3.3 3.6 v ( note 3 ) digital dvdd 2.4 3.3 avdd v pll pvdd 2.4 3.3 avdd v hp / spk - amp hvdd 2.4 3.3 avdd v note 1 . all voltages with respect to ground . note 3 . the power up sequence between avdd, dvdd, hvdd and pvdd is not critical. it is recommended that dvdd and pvdd are the same voltage as avdd in order to reduce the current at power down mode. * akm assumes no r esponsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 8 - analog characteristics ( ta=25 c ; avdd, dvdd, pvdd, hvdd = 3.3v ; a vss=dvss=pvss=hvss=0v; fs=4 4.1k hz , bick=64fs; signal frequency =1khz ; 16bit data; measurement frequency=20hz ~ 20khz; u nless otherwise specified) parameter min typ max units mic amplifier: input resistance 20 30 40 k w gain (mgain bit = ? 0 ? ) - 0 - db (mgain bit = ? 1 ? ) - 20 - db mic power supply: output voltage ( note 4 ) 2.22 2.47 2.72 v output current - - 1.25 ma input pga characteristics: input resistance (lin1, rin1 pins) 5 10 15 k w ( note 5 ) (lin2, rin2 pins) 30 60 90 k w step size 0.1 0.5 0.9 db gain control range (li n1, rin1 pins) - 8 - +27.5 db (lin2, rin2 pins) - 23.5 - +12 db adc analog input characteristics: alc1=off resolution 16 bits ( note 7 ) 0.168 0.1 98 0.228 vpp input voltage ( note 6 ) ( note 8 ) 1.68 1.98 2.28 vpp ( note 7 ) 71 79 - dbfs s/(n+d) ( - 1dbfs) ( note 8 ) - 88 - dbfs ( note 7 ) 75 83 - db d - range ( - 60dbfs, a - weig hted) ( note 8 ) - 91 - db ( note 7 ) 75 83 - db s/n (a - weighted) ( note 8 ) - 91 - db ( note 7 ) 75 90 - db interchannel isolation ( note 8 ) - 100 - db ( note 7 ) - 0.1 0.5 db interchannel gain mismatch ( note 8 ) - 0.1 0.5 db dac characteristics: resolution - - 16 bits stereo line output characteristics: r l =10k w , dac ? lout, rout output voltage ( note 9 ) 1.74 1.94 2.14 vpp s/(n+d) ( - 3dbfs) 78 88 - dbfs s/n (a - weighted) 85 92 - db interchannel isolation - 100 - db interchannel gain mismatch - 0.1 0.5 db load resistance 10 - - k w load capacitance - - 30 pf note 4 . output voltage is proportio nal to avdd voltage. vout = 0.75 x avdd. note 5 . when ipga gain is changed, this typical value changes between 8k w and 11k w (lin1, rin1), 48k w and 66k w (lin2, rin2). note 6 . input voltage is proportional to av dd voltage. vin = 0.06 x avdd )@mic in, vin = 0.6 x avdd(typ)@line in . note 7 . mic gain=20db, ipga=0db, alc1=off, int(micl)/ext(micr) ? ipga ? adc note 8 . ipga=0db, alc1=off, lin2/rin2 ? ipga ? adc note 9 . output voltage is proportional to avdd voltage. vout = 0.588 x avdd.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 9 - parameter min typ max units mono line output characteristics: r l =20k w , dac ? mout+/mout - output voltage ( note 10 ) mogn=1, - 17db - 0.31 - vpp mogn=0, +6db 3.56 3.96 4.36 vpp s/(n+d) ( - 3dbfs) mogn=1, - 17db - 76 - dbfs mogn=0, +6db 79 89 - dbfs s/n (a - weighted) mogn=1, - 17db - 79 - db mogn=0, +6db 85 95 - db load resistance mogn=1, - 17db 2 - - k w mogn=0, +6db 20 - - k w load capacitance - - 30 pf headphone - amp characteristics: r l =22.8 w , dac ? hpl/hpr, datt=0db output voltage ( note 11 ) 1.54 1.92 2.30 vpp s/(n+d) ( - 3dbfs) 60 70 - dbfs s/n (a - weighted) 80 90 - db interch annel isolation 70 85 - db interchannel gain mismatch - 0.1 0.5 db load resistance 20 - - w load capacitance (c1 in figure 2 ) - - 30 pf (c2 in figure 2 ) - - 300 pf speake r - amp characteristics: r l =8 w , btl, dac ? mout2 ? min ? spp/spn, alc2=off output voltage spkg= ? 0 ? (po=150mw) 2.47 3.09 3.71 vpp ( note 12 ) spkg= ? 1 ? (po=300mw) - 4.38 - vpp spkg= ? 0 ? (po=150mw) 50 64 - d b spkg= ? 1 ? (po=300mw) - 20 - db s/(n+d) (po=250mw) - 60 - db s/n (a - weighted) 82 90 - db load resistance 8 - - w load capacitance - - 30 pf note 10 . output voltage is proportional to avdd voltage. vout = 1.2 x avdd at full - differen tial output. vout = 0.6 x avdd at single - end output. note 11 . output voltage is proportional to a vdd voltage. vout = 0.582 x avdd. note 12 . output voltage is proportional to a vdd voltage. vout = 0.936 x avdd(ty p)@spkg= ? 0 ? , 1.327 x avdd(typ)@spkg= ? 1 ? at full - differential output. hpl/hpr pin hp-amp 47 m f c1 16 w c2 6.8 w figure 2 . headphone - amp output circuit
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 10 - parameter min typ max units beep input: beepl, beepr, beepm pin maximum input voltag e ( note 13 ) - - 1.98 vpp feedback resistance 14 20 26 k w mon o input: min pin maximum input voltage ( note 14 ) - - 1.98 vpp input resistance ( note 15 ) 12 24 36 k w mon o output: r l =10k w , dac ? mix ? mout2 output voltage ( note 16 ) - 1.94 - vpp load resistance 10 - - k w load capacitance ( note 17 ) - - 30 pf power supplies power up (pdn = ? h ? ) all circuit power - up: avdd+dvdd ( note 18 ) - 19 29 ma pvdd - 1.2 2 ma hvdd: hp - amp normal operation no output ( note 19 ) - 4 6 ma hvdd: spk - amp normal operation no output ( note 20 ) - 7 18 ma power down (pdn = ? l ? ) ( note 21 ) avdd+dvdd - 10 100 m a pvdd - 10 100 m a hvdd - 10 100 m a note 13 . beep - amp can ? t output more than this maximum voltage. note 14 . maximum input voltage is proportional to avdd voltage. vin = 0.6 x avdd. note 15 . when alc2 gain is c hanged, this typical value changes between 22k w and 26k w . note 16 . output voltage is proportional to avdd voltage. vout = 0.588 x avdd. note 17 . when the output pin drives a capacitive load, a resistor should b e added in series between the output pin and capacitive load. note 18 . pmmicl=pmmicr=pmadl=pmadr=pmdac=pmmo=pmlo=pmspk=pmhpl=pmhpr=pmvcm= pmpll=pmxtl=pmbpm=pmbps= ? 1 ? , mcko= ? 1 ? and master mode. avdd=13ma (typ.), dvdd=6ma (typ.). avd d=10ma(typ.), dvdd=6ma (typ.) at pmmicl=pmadl=pmdac=pmmo=pmlo=pmspk=pmhpl =pmhpr=pmvcm=pmpll=pmxtl=pmbpm=pmbps= ? 1 ? , pmmicr=pmadr=pmipgr= ? 0 ? , mcko= ? 1 ? and master mode . avdd=10ma (typ.), dvdd=4ma (typ.) at mcko= ? 0 ? in slave mode. note 19 . pmmicl=pmmicr=pmadl=pmadr=pmdac=pmmo=pmlo=pmhpl=pmhpr=pmvcm=pmpll= pmxtl=pmbpm=pmbps= ? 1 ? and pmspk= ? 0 ? . note 20 . pmmicl=pmmicr=pmadl=pmadr=pmdac=pmmo=pmlo=pmspk=pmvcm=pmpll=pmxtl= pmbpm =pmbps= ? 1 ? and pmhpl=pmhpr= ? 0 ? . note 21 . all digital input pins are fixed to dvdd or dvss.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 11 - filter characteristics ( ta= - 10 ~ 70 c ; a vdd , d vdd, pvdd, hvdd = 2.4 ~ 3.6v; fs=4 4.1k hz ; dem=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 22 ) 0.1db pb 0 - 17.4 khz - 1.0db - 20.0 - khz - 3.0db - 21.1 - khz stopband sb 27.0 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 65 - - db group delay ( note 23 ) gd - 17.0 - 1/fs group delay distortion d gd - 0 - m s adc digital filter (hpf): frequency response ( note 22 ) - 3.0db fr - 3.4 - hz - 0.5db - 10 - hz - 0.1db - 22 - hz dac digi tal filter: passband ( note 22 ) 0.1db pb 0 - 20.0 khz - 6.0db - 22.05 - khz stopband sb 24.1 - - khz passband ripple pr - - 0.06 db stopband attenuation sa 43 - - db group delay ( note 23 ) gd - 16.8 - 1/fs dac digital filter + scf: frequency response: 0 ~ 20.0khz fr - 0.5 - db boost filter: ( note 24 ) min 20hz fr - 5.74 - db 100hz - 2.92 - db 1khz - 0.0 - db mid 20hz fr - 5.94 - db 100hz - 4.71 - db 1khz - 0.14 - db max 20hz fr - 16.04 - db 100hz - 10.55 - db frequency response 1khz - 0.3 - db note 22 . the passband and stopband frequencies scale with fs ( system sampling rat e ) . for example, adc is pb=0.454*fs ( @-1.0db ) , dac is pb=0.454*fs ( @-0. 0 1db ) . note 23 . the calculat ed delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16 - bit data of both channels from the input register to the output register of the adc. this time includes the group delay of the hpf . for the dac, this time is from setting the 16 - bit data of both channels from the input register to the output of analog signal. note 24 . these frequency response s scale with fs . if a high - level and low frequency signal is input, the analog output clips to the full - scale.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 12 - dc characteristics ( ta= - 10 ~ 70 c ; avdd , dv d d, pvdd, hvdd=2.4 ~ 3.6 v ) parameter symbol min typ max units high - level input voltage vih 70%dvdd - - v low - level input voltage vil - - 30%dvdd v input voltage at ac coupling ( note 25 ) vac 50%dvdd - - v high - level output voltage (iout= - 200 m a) voh dvdd - 0.2 - - v low - level output voltage (except sda pin: iout=200 m a) vol - - 0.2 v (sda pin: iout=3ma) vol - - 0.4 v input leakage current iin - - 10 m a note 25 . when ac coupled capacitor is connected to mcki pin. switching characteristics ( t a= - 10 ~ 70 c ; avdd, dvdd, pvdd, hvdd = 2.4 ~ 3.6 v ; c l =2 0pf ) parameter symbol min t yp max units master clock timing crystal resonator frequency 11.2896 - 12.288 mhz external clock frequency fclk 2.048 - 12.288 mhz pulse width l ow tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns ac pulse width ( note 26 ) tacw 0.4/fclk - - ns mcko output frequency fmck 0.256 - 12.288 mhz duty cycle: except fs=32khz dmck 40 50 60 % fs=32khz at 256fs ( note 27 ) dmck - 33 - % lrck timing frequency fs 8 - 48 khz duty cycle slave mode duty 45 - 55 % master mode duty - 50 - % audio interface timing slave mode bick perio d tbck 312.5 - - ns bick pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns lrck edge to bick ? - ? ( note 28 ) tlrb 50 - - ns bick ? - ? to lrck edge ( note 28 ) tblr 50 - - ns lrck to sdto (msb) (except i 2 s mode) tlrs - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns master mode bick frequency (bf bit = ? 0 ? ) fbck - 64fs - hz (bf bit = ? 1 ? ) fbck - 32fs - hz bick duty dbck - 50 - % bick ? ? to lrck tmblr - 80 - 80 ns bick ? ? to sdto tbsd - 80 - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns note 26 . pulse width to ground level when mcki is connected to a capacitor in series and a resistor is connected to ground ( refer to figure 4 ). note 27 . pmpll bit = ? 1 ? . note 28 . bick rising edge must not occur at the same time as lrck edge.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 13 - parameter symbol min t yp max units control interface timing (4 - wire serial mode): cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cd ti hold time tcdh 40 - - ns csn ? h ? time tcsw 150 - - ns csn ? ? to cclk ? - ? tcss 50 - - ns cclk ? - ? to csn ? - ? tcsh 50 - - ns cdto delay tdcd - - 50 ns csn ? - ? to cdto hi - z tccz - - 70 ns control interface timing (i 2 c bus mode): scl cloc k frequency fscl - - 100 khz bus free time between transmissions tbuf 4.7 - - m s start condition hold time (prior to first clock pulse) thd:sta 4.0 - - m s clock low time tlow 4.7 - - m s clock high time thigh 4.0 - - m s setup time for repeated sta rt condition tsu:sta 4.7 - - m s sda hold time from scl falling ( note 29 ) thd:dat 0 - - m s sda setup time from scl rising tsu:dat 0.25 - - m s rise time of both sda and scl lines tr - - 1.0 m s fall time of both sda and scl lines tf - - 0.3 m s setup time for stop condition tsu:sto 4.0 - - m s pulse width of spike noise suppressed by input filter tsp 0 - 50 ns reset timing pdn pulse width ( note 30 ) tpd 150 - - ns pmadl or pmadr ? - ? to sdto valid ( note 31 ) tpdv - 2081 - 1/fs note 29 . data must be held long enough to bridge the 300ns - transition time of scl. note 30 . the AK4537 c an be reset by the p dn pin = ? l ? . note 31 . this is the count of lrck ? - ? from the pmadl or pmadr bit = ? 1 ? . purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the c omponents in the i 2 c system, provided the system conform to the i 2 c specifications defined by philips.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 14 - n timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil mcko dmck dmck 50%dvdd fmck figure 3 . clock timing mcki input measurement point agnd tacw t acw agnd 1/fclk 1000pf 100k w vac figure 4 . mcki ac coupling timing
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 15 - lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd tsds sdti vil tsdh vih figure 5 . audio interface timing (slave mode) lrck vih vil bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tmblr dbck figure 6 . audio interface timing (master mode)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 16 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w cdto hi-z figure 7 . write/read command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 cdto hi-z d2 figure 8 . write data input timing
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 17 - csn vih vil cclk vih vil cdti vih vil a0 cdto a1 50%dvdd tdcd d7 d6 hi-z figure 9 . read da ta output timing 1 csn vih vil tcsh cclk vih vil cdti vih tcsw vil cdto 50%dvdd d2 d1 d0 tccz hi-z figure 10 . read data output timing 2
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 18 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 11 . i 2 c bus mode timing csn vih vil tpdv sdto tpd 50%dvdd pdn vil figure 12 . power down & reset timing
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 19 - operation overview n master clock source the AK4537 requires a master clock (mclk). this master clock is input to the AK4537 by connecting a x ? tal oscillator to xti and xto pins or by inputting an external cmo s - level clock to the xti pin or by inputting an external clock that is greater than 50% of the dvdd level to the xti pin through a capacitor. when using a x ? tal oscillator , there should be capacitors between xti/xto pins and dvss. when using an external c lock, there are two choices: direct, where an external clock is input directly to the xti pin and indirect, where the external clock is input through a capacitor. master clock status pmxtl bit mckpd bit x ? tal oscillator ( figure 13 ) oscillator on 1 0 oscillator off 0 1 external clock direct input ( figure 14 ) clock is input to mcki pin. 0 0 mcki pin is fixed to ? l ? . 0 0/1 mcki pin is fixed to ? h ? . 0 0 mcki pin is h i - z 0 1 ac coupling input ( figure 15 ) clock is input to mcki pin. 1 0 clock isn?t input to mcki pin. 0 1 table 1 . master clock status by pmxtl bit and mckpd bit (1) x ? tal oscillator xti xto AK4537 25k w mckpd = "0" pmxtl = "1" c c figure 13 . x ? tal mode note: the capacitor values depend on the x ? tal oscillator used. (c : typ. 10 ~ 30pf)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 20 - (2) external clock direct input xti xto AK4537 25k w mckpd = "0" pmxtl = "0" external clock figure 14 . ex ternal clock mode (input : cmos level) note: this clock level must not exceed dvdd level. (3) ac coupling input xti xto AK4537 25k w mckpd = "0" pmxtl = "1" external clock c figure 15 . external clock mode (input : 3 50%dvdd) note: this clock level must n o t exceed d vdd level. (c : 0.1 m f)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 21 - n system clock (1) pll mode (pmpll bit = ? 1 ? ) a fully integrated analog phase locked loop (pll) generates a clock that is selected by the pll1 - 0 and fs2 - 0 bits (see table.2 and table.3). the frequency of the mcko output is selectab le via the ps1 - 0 bits registers as defined in table.4 and the mcko output enable is controlled by the mcko bit . if ps1 - 0 bits are changed before lrck is input, mcko is not output. ps1 - 0 bits should be changed after lrck is input in slave mode. the pll sho uld be powered - up after the x ? tal oscillator becomes stable or external master clock is inputted. it takes x ? tal oscillator 20ms(typ) to be stable after pmxtl bit= ? 1 ? . the pll needs 40ms lock time, whenever the sampling frequency changes or the pll is powe red - up (pmpll bit= ? 0 ? ? ? 1 ? ). lrck and bick are output from the AK4537 in master mode. when the clock input to mcki pin stops during normal operation (pmpll bit = ? 1 ? ), the internal pll continues to oscillate (a few mhz), and lrck and bick outputs go to ? l ? ( table 5 ). in slave mode, the lrck input should be synchronized with mcko. the master clock (mcki) should be synchronized with sampling clock (lrck). the phase between these clocks does not matter. lrck and bick must be present whenever the AK4537 is operating (pmadl bit = ? 1 ? , pmadr bit = ? 1 ? or pmdac bit = ? 1 ? ). if these clocks are not provided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, pla ce the AK4537 in power - down mode (pmadl bit = pmadr bit = pmdac bit = ? 0 ? ). mode pll1 pll0 mcki 0 0 0 12.288mhz default 1 0 1 11.2896mhz 2 1 0 12mhz 3 1 1 n/a table 2 . mcki input frequency (pll mode) fs2 fs1 fs0 sampling frequency 0 0 0 44.1khz default 0 0 1 22.05khz 0 1 0 11.025khz 0 1 1 48khz 1 0 0 32khz 1 0 1 24khz 1 1 0 16khz 1 1 1 8khz table 3 . sampling frequency (pll mode) mode ps1 ps0 mcko 0 0 0 256fs default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 4 . mcko frequency (pll mode, mcko bit = ? 1 ? )
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 22 - master mode (m/s pin = ? h ? ) power up power down pll unlock mcki pin frequency set by pll1 - 0 bits (refer to table 2 ) refer to table 1 frequency set by pll1 - 0 bits (refer to table 2 ) mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : unsettling bick pin bf bit = ? 0 ? : 64fs output bf b it = ? 1 ? : 32fs output ? l ? ? l ? lrck pin output ? l ? ? l ? table 5 . clock operation at master mode (pll mode) slave mode (m/s pin = ? l ? ) power up power down pll unlock mcki pin frequency set by pll1 - 0 bits (refer to table 2 ) refer to table 1 frequency set by pll1 - 0 bits (refer to table 2 ) mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : unsettling bick pin inp ut fixed to ? l ? or ? h ? externally input lrck pin input fixed to ? l ? or ? h ? externally input table 6 . clock operation at slave mode (pll mode) (2) external mode (pmpll bit = ? 0 ? ) when the pmpll bit = ? 0 ? , the AK4537 works in external clock mode. the mcko pin outputs a buffered clock of mcki input. for example, when mcki = 256fs, the sampling frequency is changeable from 8khz to 48khz ( table 7 ). the mcko bit controls mcko output enable . the frequency of mcko is selectable via register the ps1 - 0 bits as defined in table 8 . if ps1 - 0 bits are changed before lrck is input, mcko is not output. ps1 - 0 bits should be changed after lrck is input in slave mode. the master clock frequency should be changed only when the pmadl, pmadr and pmdac bits = ? 0 ? . lrck and bick are output from the AK4537 in master mode. the clock to the mcki pin must n o t stop during normal operation (pmadl bit = ? 1 ? , pmadr bit = ? 1 ? or pmdac bit = ? 1 ? ). if this clock is not p rovided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK4537 in power - down mode (pmadl bit = pmadr bit = pmdac bit = ? 0 ? ). mcki, bick and lrck clocks are requi red in slave mode. the master clock (mcki) should be synchronized with sampling clock (lrck). the phase between these clocks does not matter. lrck and bick should always be present whenever the AK4537 is in normal operation (pmadl bit = ? 1 ? , pmadr bit = ? 1 ? or pmdac bit = ? 1 ? ). if these clocks are not provided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK4537 in power - down mode (pmadl bit = pmadr bit = pmdac b it = ? 0 ? ). mode fs1 fs0 sampling frequency (fs) mcki 0 0 0 8khz ~ 48khz 256fs default 1 0 1 8khz ~ 24khz 512fs 2 1 0 8khz ~ 12khz 1024fs 3 1 1 n/a n/a table 7 . sampling frequency select (ext mode)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 23 - mode ps1 ps0 mcko 0 0 0 256fs default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 8 . mcko frequency (ext mode, mcko bit = ? 1 ? ) master mode (m/s pin = ? h ? ) power up power down mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : output ? l ? bick pin b f bit = ? 0 ? : 64fs output bf bit = ? 1 ? : 32fs output ? l ? lrck pin output ? l ? table 9 . clock operation at master mode (ext mode) slave mode (m/s pin = ? l ? ) power up power down mcko pin mcko bit = ? 0 ? : ? l ? mcko bit = ? 1 ? : out put ? l ? bick pin input fixed to ? l ? or ? h ? externally lrck pin input fixed to ? l ? or ? h ? externally table 10 . clock operation at slave mode (ext mode) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out - of - band noise. when the out - of - band noise can be improved by using higher frequency of the master clock. the s/n of the dac output through headphone amp at fs=8khz is shown in table 11 . mclk s/n (fs=8khz, a - weighted) 256fs 84db 512fs 88db 1024fs 88db table 11 . relationship between mclk and s/n of hp - amp n master mode/slave mode the m/s pin selects either master or slave modes. m/s pin = ? h ? selects master mode and ? l ? selects sl ave mode. the AK4537 outputs mcko, bick and lrck in master mode. the AK4537 outputs only mcko in slave mode, while bick and lrck must be input separately. mode mcko bick / lrck slave mode mcko = output bick = input lrck = input master mode mcko = output bick = output lrck = output table 12 . master mode/slave mode
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 24 - n system reset upon power - up, reset the AK4537 by bringing the pdn pin = ?l?. this ensures that all internal registers reset to their initial value s . the adc enters an initializ ation cycle that starts when the pmadl or pmadr bit is changed from ? 0 ? to ? 1 ? . the initializ ation cycle time is 2081/fs, or 47.2ms@fs=44.1khz . during the initializ ation cycle, the adc digital data outputs of both channels are forced to a 2's compliment, ?0?. the adc output reflects the analog input signal after the initializ ation cycle is complete . the dac does n o t require an initializ ation cycl e. n audio interface format three types of data formats are available and are se lected by setting the dif1 - 0 bits ( table 13 ). in all modes, the serial data is msb first, 2 ? s complement format. the sdto is clocked out on the falling edge of bick and the sdti is latched on the rising edge. all data formats can be used in both master and slave modes. lrck and bick are output from AK4537 in master mode, but must be input to AK4537 in slave mode. if 16 - bit data that adc outputs is converted to 8 - bit data by removing lsb 8 - bit, - 1 at 16bit data is converted to - 1 at 8 - bit data. and when the dac playbacks this 8 - bit data, - 1 at 8 - bit data will be converted to - 256 at 16 - bit data and this is a large offset. this offset can be removed by adding the offset of 128 to 16 - bit data before converting to 8 - bit data. when adc is used as monaural, the output data of powered - down channel is ? 0 ? . mode dif1 dif0 sdto (adc) sdti (dac) bick figure 0 0 0 msb justified lsb justified 3 32fs figure 16 1 0 1 msb justified msb justified 3 32fs figure 17 2 1 0 i 2 s i 2 s 3 32fs figure 18 default 3 1 1 n/a n/a n/a - table 13 . audio interface format lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 1 10 13 13 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 13 1 0 15 15 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 bick(64fs) 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 0 1 15 15 2 1 0 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 15 14 13 7 6 5 4 3 1 0 2 15 14 13 1 0 figure 16 . mode 0 timing
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 25 - lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 1 10 13 13 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 13 1 0 15 15 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 bick(64fs) 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 13 don't care 1 15 15 15 0 15 14 15 14 don't care 15:msb, 0:lsb lch data rch data 13 1 0 13 1 0 15 15 14 13 7 6 5 4 3 1 0 2 15 14 13 1 0 figure 17 . mode 1 timing lrck bick(32fs) sdto(o) sdti(i) 0 15 14 15 14 1 10 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 1 0 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 bick(64fs) 0 1 16 2 3 17 18 31 0 1 2 3 1 0 16 17 18 31 sdto(o) sdti(i) 15 14 don't care 2 15 1 15 15 15 don't care 15:msb, 0:lsb lch data rch data 14 2 1 14 2 1 8 8 8 0 0 0 0 0 15 14 7 6 5 4 3 2 1 0 8 15 14 2 1 0 figure 18 . mode 2 timing n digital high pass filter the adc has a digital high p ass filter for dc offset cancellation. the cut - off frequency of the hpf is 3.4hz (@fs=44.1khz) and scales with sampling rate (fs).
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 26 - n mic gain amplifier AK4537 has a gain amplifier for microphone input. this gain is 0db or 20db, selected by the mgain b it ( table 14 ). the typical input impedance is 30k w . mgain bit input gain 0 0db 1 +20db default table 14 . mic input gain the mic gain amp of the AK4537 supports the following three cases: micoutl micoutr int ext msel= ? 0 ? internal mic pmmicl bit = ? 1 ? pmmicr bit = ? 0 ? external mic figure 19 . internal mic (mono) micoutl micoutr int ext msel= ? 1 ? external mic pmmicl bit = ? 1 ? pmmicr bit = ? 0 ? internal mic figure 20 . external mic (mono) micoutl micoutr micl micr msel= ? 0 ? mic lch pmmicl bit = ? 1 ? pmmicr bit = ? 1 ? mic rch figure 21 . stereo mic n mic power the mpi a nd mpe pins supply power for the microphone. these output voltages are 0.75 x avdd (typ) and the maximum output current is 1.25ma.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 27 - n manual mode the AK4537 becomes a manual mode at alc1 bit = ? 0 ? . this mode is used in the case shown below. 1. after ex iting reset state, set up the registers for the alc1 operation (ztm1 - 0, lmth and etc) 2. when the registers for the alc1 operation (limiter period, recovery period and etc) are changed. for example ; when the change of the sampling frequency . 3. when ipga is used as a manual volume. when writing to the ipgal6 - 0 and ipgar6 - 0 bits continually , the control register should be written by an interval more than zero crossing timeout (the write operation interval between ipgal6 - 0 and ipgar6 - 0 bits also should be m ore than zero crossing timeout). when ipgac bit is ? 0 ? , the write operation interval from ipgal6 - 0 bits to ipgar6 - 0 bits is no care. therefore, the auto increment function of i 2 c bus is available at ipgac = ? 0 ? . n mic - alc operation the alc (automatic le vel control) of mic input is done by alc1 block when alc1 bit is ? 1 ? . when pmmicl bit = ? 1 ? and pmmir bit = ? 1 ? , the ipga is set to the same value for both channels. [1] alc1 limiter operation when the alc1 limiter is enabled, and ipga lch or rch output exce eds the alc1 limiter detection level (lmth), the ipga value is attenuated by the amount defined in the alc1 limiter att step (lmat1 - 0 bits) automatically. when the zelm bit = ? 1 ? , the timeout period is set by the ltm1 - 0 bits. the operation for attenuation is done continuously until both lch and rch input signal levels become lmth or less. if the alc1 bit does not change into ? 0 ? after completing the attenuation, the attenuation operation repeats while lch or rch input signal level equals or exceeds lmth. when the zelm bit = ? 0 ? , the timeout period is set by the ztm1 - 0 bits. this enables the zero - crossing attenuation function so that the ipga value is attenuated at the zero - detect points of the waveform. [2] alc1 recovery operation the alc1 recovery refers to the amount of time that the AK4537 will allow both lch and rch signal to exceed a predetermined limiting value prior to enabling the limiting function. the alc1 recovery operation uses the wtm1 - 0 bits to define the wait period used after completing an alc 1 limiter operation. if lch or rch input signals are lower than the ? alc1 recovery waiting counter reset level ? , the alc1 recovery operation starts. the ipga value increases automatically during this operation up to the reference level (ref6 - 0 bits). the a lc1 recovery operation is done at a period set by the wtm1 - 0 bits. zero crossing is detected during wtm1 - 0 period, the alc1 recovery operation waits wtm1 - 0 period and the next recovery operation starts. during the alc1 recovery operation, when lch or rch input signal level exceeds the alc1 limiter detection level (lmth), the alc1 recovery operation changes immediately into an alc1 limiter operation. in the case of (ipga lch and rch output level) < (limiter detection level ) and (ipga lch and rch output lev el) 3 (recovery waiting counter reset level) during the alc1 recovery operation, the wait timer for the alc1 recovery operation is reset. therefore, in the case of (ipga lch or rch output level) < (recovery waiting counter reset level), the wait timer for the alc1 recovery operation starts. the alc1 operation corresponds to the impulse noise. when the impulse noise is input, the alc1 recovery operation becomes faster than a normal recovery operation.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 28 - [3] example of alc1 operation table 15 shows the example s of the alc1 setting. in case of this examples, alc1 operation starts from 0db. fs=8khz fs=16khz fs=44.1khz register name comment data operation data operation data operation lmth limiter detection level 1 - 4dbfs 1 - 4dbfs 1 - 4dbfs ltm1 - 0 limiter ope ration period at zelm = 1 00 don ? t use 00 don ? t use 00 don ? t use zelm limiter zero crossing detection 0 enable 0 enable 0 enable ztm1 - 0 zero crossing timeout period 00 16ms 01 16ms 10 11.6ms wtm1 - 0 recovery waiting period *wtm1 - 0 bits should be the same data as ztm1 - 0 bits 00 16ms 01 16ms 10 11.6ms ref6 - 0 maximum gain at recovery operation 47h +27.5db 47h +27.5db 47h +27.5db ipgal6 - 0, ipgar6 - 0 gain of ipga at alc1 operation start 10h 0db 10h 0db 10h 0db lmat1 - 0 limiter att step 00 1 step 00 1 step 00 1 step ratt recovery gain step 0 1 step 0 1 step 0 1 step alc1 alc1 enable bit 1 enable 1 enable 1 enable table 15 . example of the alc1 setting the following registers should not be changed during the alc1 operation. these bits should be changed after the alc1 operation is finished by alc1 bit = ? 0 ? or pmmic bit = ? 0 ? . ltm1 - 0, lmth, lmat1 - 0, wtm1 - 0, ztm1 - 0, ratt, ref6 - 0, zelm bits ipga gain at alc1 operation start can be changed from the default value of ipgal6 - 0 bits while p mmicl, pmmicr, pmipgl or pmipgr bit is ? 1 ? and alc1 bit is ? 0 ? . when alc1 bit is changed from ? 1 ? to ? 0 ? , ipga holds the last gain value set by alc1 operation. manual mode * the value of ipga should be t he same or smaller than ref ? s wr (ztm1 - 0, wtm1 - 0, ltm1 - 0) wr (ref6 - 0) wr (ipga6 - 0) alc1 operation wr (alc1= ? 1 ? , lmat1 - 0, ratt, lmth, zelm) example: limiter = zero crossing enable recovery cycle = 16ms @ fs= 8khz limiter and recovery step = 1 maximum gain = +27.5db limiter detection level = - 4dbfs alc2 bit = ? 1 ? ( default ) (1) addr=08h, data=00h (2) addr=0ah, data=47h (4) addr=09h, data=61h (3) addr=0bh&0fh, data=10h note : wr : write figure 22 . registers se t - up sequence at alc1 operation
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 29 - n de - emphasis filter the AK4537 includes the digital de - emphasis filter (tc = 50/15 m s) by iir filter. s etting the dem1 - 0 bits enables the de - emphasis filter ( table 16 ). dem1 dem0 mode 0 0 44.1kh z 0 1 off default 1 0 48khz 1 1 32khz table 16 . de - emphasis control n bass boost function the bst1 - 0 bits control the amount of low frequency boost applied to the dac output signal ( table 17 ) . if t he bst1 - 0 bits are set to ? 10 ? (mid level), use a 47 m f capacitor for ac - coupling. if the boosted signal exceeds full scale, the analog output clips to the full scale. figure 10 shows the boost frequency response at ? 20db signal input. figure 23 . boost frequency (fs=44.1khz) bst1 bst0 mode 0 0 off default 0 1 min 1 0 mid 1 1 max table 17 . low frequency boost control boost frequency (fs=44.1khz) -25 -20 -15 -10 -5 0 0.01 0.1 1 10 frequency [khz] output level [db] min mid max
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 30 - n digital attenuator the AK4537 has a channel - independent digital attenuator ( 256 levels, 0.5db step, mute). the attenuation level of each channel can be set by the attl/r7 - 0 bits. when the dattc bit = ? 1 ? , the attl7 - 0 bits control both lch and rch attenuation levels. when the dattc bit = ? 0 ? , the attl7 - 0 bits control lch level and attr7 - 0 bits control rch level. this attenuator has a soft transition function. it takes 1061/fs from 00h to ffh. attl/r7 - 0 attenuation 00h 0db default 01h - 0.5db 02h - 1.0db 03h - 1.5db : : : : fdh - 126.5db feh - 127.0db ffh mute ( - ) tab le 18 . datt code table n soft mute soft mute operation is performed in the digital domain. when the smute bit goes to a ? 1 ? , the output signal is attenuated by - ( ? 0 ? ) during the cycle set by the tm1 - 0 bits. when the smute bit i s returned to ? 0 ? , the mute is cancelled and the output attenuation gradually changes to 0db during the cycle set of the tm1 - 0 bits. if the soft mute is cancelled within the cycle set by the tm1 - 0 bits after starting the operation, the attenuation is disco ntinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the signal transmission ( figure 24 ). the soft mute function is independent of output volume and cascade connect ed between both functions. smute bit attenuation tm1-0 bit 0db - tm1-0 bit gd gd (1) (2) (3) analog output figure 24 . soft mute function (1) the output signal is attenuated until - ( ? 0 ? ) by the cycle set by the tm1 - 0 bits. (2) analog output corresponding to digital input has the group d elay (gd). (3) if the soft mute is cancelled within the cycle of setting the tm1 - 0 bits, the attenuation is discounted and returned to 0db(the set value).
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 31 - n beep input when the pmbps bit is set to ? 1 ? , the stereo beep input is powered up. and when the bpsh p bit is set to ? 1 ? , the input signals from the beepl and beepr pins are mixed to headphone outputs. when the bpssp bit is set to ? 1 ? , the signal of (beepl + beepr)/2 is input to speaker - amp. when the pmbpm bit is set to ? 1 ? , mono beep input is powered up. and when the bpmhp bit is set to ? 1 ? , the input signal from the beepm pin to headphone - amp. when the bpmsp bit is set to ? 1 ? , the signal from the beepm pin is input to speaker output. the external resisters ri adjust the signal level of each beep input th at are mixed to headphone and speaker outputs. the signal from the beepm pin is mixed to the headphone - amp through a ? 20db gain stage. the signal from the beepm pin is mixed to the speaker - amp without gain. the internal feedback resistance is 20k 30% w . beepl ri rf = 20k w beepr ri rf = 20k w AK4537 beepm ri rf = 20k w bpmhp spk mix hpl mix hpr mix bpshp bpshp -20db bpmsp bpssp 1/2 1/2 figure 25 . block diagram of beep pins
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 32 - n headphone output power supply voltage for the headphone - amp is supplied from the hvdd pin and centered on the hvdd/2 voltage. the headphone output load res istance is min.20 w . when the pmhpl and pmhpr bits are ? 0 ? , the common voltage of headphone - amp falls and the outputs (hpl and hpr pins) go to ? l ? (hvss). when the pmhpl and pmhpr bits are ? 1 ? , the common voltage rises to hvdd/2. a capacitor between the mut et pin and ground reduces pop noise at power - up . [example] : a capacitor between the mutet pin and ground = 1.0 m f: time constant of rise/fall time: t = 100ms when hpl and hpr bits are ? 1 ? , the headphone - amp is powered - down, and the outputs (hpl and hpr p ins) go to ? l ? (hvss). pmhpl/r bit hpl/r bit hpl/r pin (1) (2) (4) (3) figure 2 6 . power - up/power - down timing for headphone - amp (1) headphone - amp power - up (hpl, hpr bit= ? 0 ? ). the outputs are still hvss. (2) headphone - amp common voltage rise up (pmhpl, pmhp r bit= ? 1 ? ). common voltage of headphone - amp is rising . this rise time depends on the capacitor value connected with the mutet pin. the time constant is t = 100k x c when the capacitor value on mutet pin is ? c ? . (3) headphone - amp common voltage fall down (pmhp l, pmhpr bit= ? 0 ? ). common voltage of headphone - amp is fall ing . this fall time depends on the capacitor value connected with the mutet pin. the time constant is t = 100k x c when the capacitor value on mutet pin is ? c ? . (4) headphone - amp power - down (hpl, hpr b it= ? 1 ? ). the outputs are hvss. if the power supply is switched off or headphone - amp is powered - down before the common voltage goes to hvss, some pop noise occurs.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 33 - the cut - off frequency of headphone - amp output depends on the external resistor and capacit or used . table 19 shows the cut off frequency and the output power for various resistor/capacitor combinations. the headphone impedance r l is 16 w . output powers are shown at hvdd = 2.7, 3.0 and 3.3v. the output voltage of headphone is 0.6 x avdd (vpp). when an external resistor r is smaller than 12 w , put an oscillation prevention circuit (0.22 m f 20% capacitor and 10 w 20% resistor ) because it has the possibility that headphone - amp oscillates . AK4537 hp-amp 16 w headphone 10 w 0.22 m r c figure 27 . external circuit example of headphone output power [mw] r [ w ] c [ m f] fc [hz] boost=off fc [hz] boost=mid 2.7v 3.0v 3.3v 6.2 47 152.5 63 10.0 12.4 15.0 16 47 105.8 43 4.8 6.0 7.2 6.2 100 71.2 27 10.0 12.4 15.0 16 100 49.7 20 4.8 6.0 7.2 table 19 . external circuit example
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 34 - n speaker output the output signal from analog volume is converted into a mon o signal [(l+r)/2] and this signal is input to the speaker - amp via the alc2 circuit. this speaker - amp is a mono output controlled by btl and can output a maximum of 300mw@spkg= ? 0 ? and alc2= ? 0 ? at 8 w load when hvdd = 3.3v. spkg alc2 po(max) 0 x 150mw default 0 300mw 1 1 250mw table 20 . spk - amp maximum output power (x: don ? t care) speaker blocks (mout2, alc2 and speaker - amp) can be powered up/down by controlling the pmspk bit. when the pmspk bit is ? 0 ? , the mout2, spp and spn pins are placed in a hi - z state. when the spps bit is ? 0 ? , the speaker - amp enters power - save - mode . in this mode, the spp pin is placed in a hi - z state and the spn pin goes to hvdd/2 voltage . and then the speaker output gradually changes to the hvdd/2 voltage and this mode can reduce pop noise at power - up. when the AK4537 is powered down, pop noise can be also reduced by first entering power - save - mode. pmspk bit spps bit spp pin spn pin hvdd/2 hvdd/2 hi-z hi-z hi-z hi-z figure 28 . power - up/power - down timing for speaker - amp n mono output (mout2 pin) the mixed lch/rch signal of dac is output from the mout2 pin. whe n the mout2 bit is ? 0 ? , this output is off and the mout2 pin is forced to vcom voltage. the load impedance is 10k w (min.). when the pmspk bit is ? 0 ? , the speaker - amp enters power - down - mode and the output is placed in a hi - z state.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 35 - n stereo line output ( lout/rout pins) att+dac mic in 0db/+20db ipga lch att ?mic l ? ? dahs ? lout pin rout pin figure 29 . stereo line output when dahs bit is ? 1 ? , lch/rch signal of dac is output from the lout/rout pins which is single - ended. when micl bit is ? 1 ? , lch signal of ipga is output fr om lout/rou pins. the load impedance is 10k w (min.). when the pmlo bit is ? 0 ? , the stereo line output enters power - down - mode and the output is placed in a hi - z state. when the pslo bit is ? 0 ? at pmlo bit is ? 1 ? , stereo line output becomes power - save - mode a nd the lout/rout pins are forced to 0.45 x avdd voltage. when pslo bit is ? 1 ? at pmlo bit is ? 1 ? , stereo line output is normal operation. attl7 - 0 and attr7 - 0 bits set the volume control of dac output. atts3 - 0 bits set the volume control of ipga lch output . n mono output (mout+/mout - pins) att+dac mic in 0db/+20db ipga lch mout+ 1/2 mout - - 17db/+6db 1/2 ? mic m ? ? damo ? ? m ogn ? att figure 30 . mono line output when damo bit is ? 1 ? , mono mixer mixes lch and rch signal from dac. this mixed signal is output to mono line output that is differential output. when micm bit is ? 1 ? , lch signal from ipga is output to mono line output. either mout+ or mout - pin can be used as single - ended output pin. the load impedance is 20k w (min.). when the pmmo bit is ? 0 ? , the mono line output enters power - down - mode an d the output is placed in a hi - z state. attl7 - 0 and attr7 - 0 bits set the volume control of dac output. attm bit sets the volume control of ipga lch output. amp for mono line output has 6db gain and - 17db gain that are set by the mogn bit.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 36 - n alc2 opera tion (alc2 bit = ? 1 ? ) input resistance of the alc2 is 24k w (typ) and centered around vcom voltage, and the input signal level is ? 3.1dbv. (see figure 31 and figure 32 . 0dbv=1v rms=2.828vpp) the limiter detection level is proportional to hvdd. the output level is limited by the alc2 circuit when the input signal exceeds ? 5.2dbv (=fs - 1.9db@hvdd=3.3v). when a continuous signal of ? 5.2dbv or greater is input to the alc2 circuit, th e change period of the alc2 limiter operation is set by the rotm bit and the attenuation level is 0.5db/step. the alc2 recovery operation uses zero crossings and gains of 1db/step. the alc2 recovery operation is done until the input level of the speaker - a mp goes to ? 7.2dbv (=fs-3.9db@hvdd=3.3v) . the rotm bit sets the alc2 recovery operation period . when the input signal is between ? 5.2dbv and ? 7.2dbv, the alc2 limiter or recovery operations are not done. when the pmspk bit changes from ? 0 ? to ? 1 ? , the ini tilization cycle (2048/fs = 46.4ms @fs=44.1khz at rotm bit = ? 0 ? , 512/fs = 11.4ms @fs=44.1khz at the rotm bit = ? 1 ?) starts. the alc2 is disabled during the initilization cycle and the alc2 starts after completing the initilization cycle. parameter alc 2 l imiter operation alc2 recovery operation operation start level - 5.2dbv - 7.2dbv rotm bit = ? 0 ? 2/fs = 45 m s@fs=44.1khz 2048/fs = 46.4ms@fs=44.1khz period rotm bit = ? 1 ? 2/fs = 181 m s@fs=11.025khz 512/fs = 46.4ms@fs=11.025khz zero - crossing detection x o ( timeout = 2048/fs) att/gain 0.5db step 1db step table 21 . limiter /recovery of alc2 at hvdd=3.3v -15.3dbv fs fs-12db 0dbv fs-2.1db = -5.2dbv -1.2dbv full-differential -3.3dbv -10dbv -5.2dbv -20dbv -30dbv -23.3dbv -8db -15.3dbv -11.3dbv -3.3dbv fs-4.1db = -7.2dbv +8.1db +16.1db +4.1db -1.9db +6.0db -8db single-ended datt dac alc2 spk-amp 0.8dbv(150mw@8ohm) +6.0db -7.2dbv figure 31 . speaker - amp output level diagram (hvdd=3.3v, datt= - 8.0db , spkg bit = ? 0 ? , alc2= ? 1 ? )
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 37 - -15.3dbv fs fs-12db 0dbv fs-2.1db = -5.2dbv 1.0dbv full-differential -3.3dbv -10dbv -3.0dbv -20dbv -30dbv -23.3dbv -8db -15.3dbv -11.3dbv -3.3dbv fs-4.1db = -7.2dbv +8.1db +16.1db +4.1db -1.9db +8.2db -8db single-ended datt dac alc2 spk-amp 3.0dbv(250mw@8ohm) +8.2db +2.2db -5.0dbv +2.2db figure 32 . speaker - amp output level diagram (hvdd=3.3v, datt= - 8.0db, spkg bit= ? 1 ? , alc2= ? 1 ? )
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 38 - n serial control interface (1) 4 - wire serial control mode (i2c pin = ? l ? ) internal r egisters may be written by using the 4 - wire p interface pins ( csn , cclk, cdti and cdto). the data on this interface consists of a 2 - bit chip address, read/write, register address (msb first, 5bits) and control data (msb first, 8bits). the chip address hig h bit is fixed to ? 1 ? and the lower bit is set by the cad0 pin. address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. after a low - to - high transition of csn , data is latched for write operations and cdto bit outputs hi - z. the clock speed of cclk is 5mhz (max). the value of internal registers is initialized at pdn pin = ? l ? . csn cclk cdti 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 c1 c0 r/w a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 cdto hi-z write cdti c1 c0 r/w a4 a3 a2 a1 a0 cdto hi-z read d7 d6 d5 d4 d3 d2 d1 d0 hi-z c1 - c0 : chip address (c1="1", c0=cad0) r/w : read / write ("1" : write, "0" : read) a4 - a0 : register address d7 - d0 : control data figure 33 . serial control i/f timing
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 39 - (2) i 2 c - bus control mode (i2c pin = ? h ? ) t he AK4537 supports the standard - mode i 2 c - bus (max: 100khz). the AK4537 does n o t support a fast - mode i 2 c - bus system (max: 400khz). (2) - 1. write operations figure 34 shows the data transfer sequence for the i 2 c - bus mo de. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicat es a start condition ( figure 40 ) . after the start condition, a slave address is sent. this address is 7 bits long followed by an eighth bit that is a data direction bit (r/w). the most significant five bits of the slave address are fixed as ? 00 10 0 ?. the next two bits are cad1 and cad0 (device address bits ) . these two bits identify the specific device o n the bus. the hard - wired input pins (cad1 and cad0 pin s ) set the se device address bits ( figure 35 ) . if the slave address matches that of the AK4537, the AK4537 generates an acknowledge and the operation is executed. the master must generate the acknowledge - related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 41 ). a r/w bit value of ? 1 ? indicates that the read operation is to be executed . a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK4537. the format is msb first, and those most significant 3 - bits are fixed to zeros ( figure 36 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 37 ). the AK4537 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condit ion generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 40 ) . the AK4537 can perform more than one byte write operation per sequence . after receipt of the third byte the AK4537 generates an acknowledge and awaits the next data. t he master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal 5 - bit add ress counter is incremented by one , and the next data is automatically taken into the next address. only write to address 00h to 10h. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line c an only change when the clock signal on the scl line is low ( figure 42 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 34 . data transfer sequence at the i 2 c - bu s mode 0 0 1 0 0 cad1 cad0 r/w ( those cad1/0 should match with cad1/0 pins) figure 35 . the first byte 0 0 0 a4 a3 a2 a1 a0 figure 36 . the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 37 . byte structure after the second byte
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 40 - (2) - 2. read operations set the r /w bit = ? 1 ? for the read operation of the AK4537 . after transmission of data, t he master can read the next address ? s data by generating an acknowledge instead of terminating t he write cycle after the receipt of the first data word. after receiving each data packet the internal 5 - bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 1fh prior to generati ng a stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the AK4537 supports two basic read operations: current address read and random address read . (2) - 2 - 1. current address read t he AK4537 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address n, the next current read operation would access data from the address n+1. after rece ipt of the slave address with r/w bit set to ? 1 ?, the AK4537 generates an acknowledge , transmits 1 - byte of data to the address set by the internal address counter and increments the internal address counter by 1 . if t he master does not generate an acknowle dge to the data but instead generate s a stop condition, the AK4537 ceases transmission . sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 38 . current address read (2) - 2 - 2. random address read the random read operation allow s the master to acce ss any memory location at random. prior to issuing the slave address with the r/w bit set to ? 1 ?, the master must first perform a ?dummy? write operation. the master issues a start request , a slave address ( r/w bit = ? 0 ? ) and then the register address to r ead. after the register address i s acknowledge d , the master immediately reissues the start request and the slave address with the r/w bit set to ? 1 ?. the AK4537 then generates an acknowledge , 1 byte of data and increments the internal address counter by 1. if t he master does not generate an acknowledge to the data but instead generate s a stop condition, the AK4537 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 39 . random address read
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 41 - scl sda stop condition start condition s p figure 40 . start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 41 . acknowledge on the i 2 c - bus scl sda data line stable; data valid change of data allowed figure 42 . bit transfer on the i 2 c - bus
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 42 - n register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmvcm pmbps pmbpm pmlo pmmo pmipgl pmmicl pmadl 01h power management 2 mckpd pmxtl pmpll spkg pmspk pmhpl pmhpr pmdac 02h signal select1 mogn psmo damo micm bpssp bpmsp alcs mout2 03h signal select2 dahs pslo 0 micl bpshp bpmhp hpl hpr 04h mode control 1 pll1 pll0 ps1 ps0 mcko bf dif1 dif0 05h mode control 2 fs2 fs1 fs0 0 0 hpm loop spps 06h dac control tm1 tm0 smute dattc bst1 bst0 dem1 dem0 07h mic control 0 0 ipgac mpwre mpwri micad msel mgain 08h timer select 0 rotm ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 09h alc mode control 1 0 alc2 alc1 zelm lmat1 lmat0 ratt lmth 0ah alc mode control 2 0 ref6 ref5 ref4 ref3 ref2 ref1 ref0 0bh lch input pga control 0 ipgal6 ipgal5 ipgal4 ipgal3 ipgal2 ipgal1 ipgal0 0ch lch digital att control attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 0dh rch digital att control attr7 attr6 attr5 attr4 attr3 attr2 attr1 attr0 0eh volume control attm atts2 atts1 atts0 0 0 0 0 0fh rch input pga control 0 ipgar6 ipgar5 ipgar4 ipgar 3 ipgar2 ipgar1 ipgar0 10h power management 3 0 0 0 inr inl pmipgr pmmicr pmadr pdn pin = ? l ? resets the registers to their default values. note: unused bits must contain a ? 0 ? value. note: only write to address 00h to 10h.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 43 - n register definitions a ddr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmvcm pmbps pmbpm pmlo pmmo pmipgl pmmicl pmadl r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmadl: adc lch block power control 0: power down (default) 1: power up wh en the pm ad l or pmadr bit changes from ?0? to ?1?, the initializ ation cycle (2081/fs=47.2ms @44.1khz) starts. after initializing , digital data of the adc is output. analog digital pmadl pmadr lch rch l/r 0 0 power down power down power down 0 1 power down power up power up 1 0 power up power down power up 1 1 power up power up power up table 22 . adc block power control pmmicl: mic power and ipga lch block power control 0: power down (default) 1: power up pmipgl: ipga l ch block power control 0: power down (default) 1: power up ipga lch block is powered up if pmmicl or pmipgl bit is ? 1 ? (see table 23 ). pmmicl pmipgl mic - amp ipga 0 0 power down power down 0 1 power down power up 1 0 power u p power up 1 1 power up power up table 23 . mic - amp and ipga lch block power control pmmo: mono line out power control 0: power down (default) 1: power up pmlo: stereo line out power control 0: power down (default) 1: power up pmbpm: mono beep in power control 0: power down (default) 1: power up even if pmbpm= ? 0 ? , the path is still connected between beepm and hp/spk - amp. bpmhp and bpmsp bits should be set to ? 0 ? to disconnect these paths, respectively. pmbps: stereo beep in power control 0: power down (default) 1: power up even if pmbps= ? 0 ? , the path is still connected between beepl/r and hp/spk - amp. bpshp and bpssp bits should be set to ? 0 ? to disconnect these paths, respectively.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 44 - pmvcm: vcom block powe r control 0: power down (default) 1: power up each block can be powered down respectively by writing ? 0 ? in each bit. when the pdn pin is ? l ? , all blocks are powered down. when all bits except mckpd bit are ? 0 ? in the 00h, 01h and 10h addresses, all blocks are powered down. the register values remain unchanged. ipga gain is reset when pmmicl=pmmicr=pmipgl=pmipgr= ? 0 ? (refer to the ipgal6 - 0 and ipgar6 - 0 bits description). when any of the blocks are powered up, the pmvcm bit must be set to ? 1 ? . mclk, bick and lrck must always be present unless pmmicl=pmmicr=pmipgl=pmipgr=pmadcl =pmadr=pmdac=pmspk= ?0? or pdn pin = ? l ? . the paths from beep to hp - amp and spk - amp can operate without these clocks. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power man agement 2 mckpd pmxtl pmpll spkg pmspk pmhpl pmhpr pmdac r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 pmdac: dac block power control 0: power down (default) 1: power up pmhpr: rch of headphone - amp common voltage power control 0: power down (default) 1: power up pmhpl: lch of headphone - amp common voltage power control 0: power down (default) 1: power up pmspk: speaker block power control 0: power down (default) 1: power up spkg: select speaker - amp output power (8 w lo ad) 0: 150mw (default) 1: 300mw(alc2 = ? 0 ? ) or 250mw(alc2 = ? 1 ? ) pmpll: pll block power control select 0: ext mode and power down (default) 1: pll mode and power up pmxtl: x ? tal oscillation block power control 0: power down (default) 1: pow er up mckpd: xti pin pull down control 0: master clock input enable 1: pull down by 25k w (default)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h signal select 1 mogn psmo damo micm bpssp bpmsp alcs mout2 r/w r/w r/w r/w r/w r/w r/w r/w r/w defa ult 0 0 0 0 0 0 0 0 mout2: mout2 output enable ( mixing = ( l+r ) /2 ) 0: off (default) 1: on when the mout2 bit = ? 0 ? , the mout2 pin outputs vcom voltage. the mout2 pin outputs signal at the mout2 bit = ? 1 ? . this bit is valid at the pmspk bit = ? 1 ? . hi - z is output at the pmspk bit = ? 0 ? . alcs: alc2 to speaker - amp enable 0: off (default) 1: on alc 2 output signal is mixed to speaker - amp at the alcs bit = ? 1 ? . bpmsp: beep m to speaker - amp enable 0: off (default) 1: on mono beep signal (beepm pin) is mixed to speaker - amp at the bpmsp bit = ? 1 ?. bpssp: beep l/beepr to speaker - amp enable 0: off (default) 1: on stereo beep signal s (beepl/beepr pins) are mixed to speaker - amp at the bpssp bit = ? 1 ?. micm: ipga lch to mout+/mout - enable 0: off (default) 1: on ipga lch output signal is output through mono line output (mout+/mout - pins) at the micm bit = ? 1 ?. damo: dac to mout+/mout - enable 0: off (default) 1: on dac output signal is output through mono line output (mout+/mout - pins) at the damo bit = ? 1 ?. ps mo: mout+/mout - output enable ( mixing = ( l+r ) /2 ) 0: power save mode (default) 1: normal operation when the psmo bit = ? 0 ? , mono line output is in power save mode and the mout+ and mout - pins output 0.45 x avdd voltage. mogn: gain control for mono output 0: +6db (default) 1: - 17db
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 46 - dac dahs beepm beepl bpmsp beepr bpssp mix mout2 alc2 alcs spk figure 43 . speaker - amp switch control
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 47 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 dahs pslo 0 micl bpshp bpmhp hpl hpr r/w r/w r/w rd r/w r/w r/w r/w r /w default 0 0 0 0 0 0 1 1 hpr: rch of headphone - amp power control 0: normal operation 1: off(default) hpl: lch of headphone - amp power control 0: normal operation 1: off(default) bpmhp: beep m to headphone - amp enable 0: off (default) 1: on mono beep signal (beepm) is mixed to headphone - amp at the bpmhp bit = ? 1 ?. bpshp: beepl/beepr to headphone - amp enable 0: off (default) 1: on stereo beep signal s (beepl/beepr) is mixed to headphone - amp at the bpshp bit = ? 1 ?. micl: ipga lch to stereo line output, headphone - amp and mout2 enable 0: off (default) 1: on ipga lch signal is mixed to stereo line output, headphone - amp and mout2 at the dahs bit = ? 1 ? . pslo: select lineout 0: off. power - save - mode. output 0.45 x avdd voltage. ( default ) 1: normal op eration pslo bit is enable when pmlo= ? 1 ? . dahs: dac to stereo line output, headphone - amp and mout2 enable 0: off (default) 1: on dac signal is mixed to stereo line output, headphone - amp and mout2 at the dahs bit = ? 1 ? . dac dahs beepm beepl bpmhp beepr hpl hpr mute mute bpshp hpr hpl fig ure 44 . headphone - amp switch control
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 48 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 pll1 pll0 ps1 ps0 mcko bf dif1 dif0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 dif1 - 0: audio interface for mat select (see table 13 ) default: ? 10 ? (adc: i 2 s, dac: i 2 s) bf: bick frequency select at master mode 0: 64fs (default) 1: 32fs this bit is invalid in slave mode. mcko: master clock output enable 0: disable (default) 1 : enable ps1 - 0: output master clock select (see table 4 , table 8 ) default: ? 00 ? (256fs) pll1 - 0: input master clock select at pll mode (see table 2 ) default: ? 00 ? (12.288mhz)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 49 - add r register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 2 fs2 fs1 fs0 0 0 hpm loop spps r/w r/w r/w r/w rd rd r/w r/w r/w default 0 0 0 0 0 0 0 0 spps: speaker - amp power - save - mode 0: power save mode (default) 1: normal operation when the spps bit = ? 1 ? , the speaker - amp is in power - save - mode and the sp p pin becomes hi - z and sp n pin is se t to hvdd/2 voltage. when the pmspk bit = ? 1 ? , this bit is valid. after the pdn pin changes from ? l ? to ? h ? , the pmspk bit is ? 0 ? , which powers down speaker - amp. loo p: loopback on/off 0: off (default) 1: on when this bit is ? 1 ? , the adc output is passed to the dac input internally. the external input data to dac is ignored. hpm: mono output select of headphone 0: stereo (default) 1: mono. when the hpm bit = ? 1 ? , (l+r)/2 signals are output to lch and rch of the headphone - amp. both pmhpl and pmhpr bits should be ? 1 ? when hpm bit is ? 1 ? . fs2 - 0: sampling frequency modes (see table 3 , table 7 ) default: ? 000 ? (fs=44. 1khz)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 50 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h dac control tm1 tm0 smute dattc bst1 bst0 dem1 dem0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 1 dem1 - 0: de - emphases response (see table 16 ) default: ? 01 ? (off) bst1 - 0: select low frequency boost function (see table 17 ) default: ? 00 ? (off) dattc: dac digital attenuator control mode select 0: independent 1: dependent (default) when dattc= ? 1 ? , attl7 - 0 bits control both lch and rch at same time. attr7 - 0 bits are n o t changed when the attl7 - 0 bits are written. smute: soft mute control 0: normal operation (default) 1: dac outputs soft - muted soft mute operation is independent of digital attenuator and is performed in the digita l domain. tm1 - 0: soft mute time select (see table 24 ) default: ? 00 ? (1024/fs) tm1 tm0 cycle 0 0 1024/fs default 0 1 512/fs 1 0 256/fs 1 1 128/fs table 24 . soft mute time setting
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 51 - addr registe r name d7 d6 d5 d4 d3 d2 d1 d0 07h mic/hp control 0 0 ipgac mpwre mpwri micad msel mgain r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 mgain: 1 st mic - amp gain control 0: 0db 1: +20db (default) msel: microphone select 0: internal mic (d efault) 1: external mic micad: switch control from mic in to adc 0: off (default) 1: on alc1 output signal is input to adc when micad bit = ? 1 ? . mpwri: power supply control for internal microphone 0: off (default) 1: on the setting of mpwri is enabled when pmmicl bit = ? 1 ? . mpwre: power supply for external microphone 0: off (default) 1: on the setting of mpwre is enabled when pmmicl bit = ? 1 ? . ipgac: ipga control mode select 0: dependent (default) 1: independent when ipgac= ? 1 ? , ipgal6 - 0 bits co ntrol both lch and rch at same time. ipgar6 - 0 bits are n o t changed when the ipgal6 - 0 bits are written.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 52 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h timer select 0 rotm ztm1 ztm0 wtm1 wtm0 ltm1 ltm0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 ltm1 - 0: alc1 limiter operation period at zero crossing disable (zelm bit = ? 1 ? ) (see table 25 ) the ipga value is changed immediately. when the ipga value is changed continuously, the change is done by the period specified by the ltm1 - 0 bits. default is ? 00 ? (0.5/fs). alc1 limiter operation period ltm1 ltm0 8khz 16khz 44.1khz 0 0 0.5/fs 63 m s 31 m s 11 m s default 0 1 1/fs 125 m s 63 m s 23 m s 1 0 2/fs 250 m s 125 m s 45 m s 1 1 4/fs 500 m s 250 m s 91 m s table 25 . alc1 limiter operation period at zero crossing disable (zelm bit = ? 1 ? ) wtm1 - 0: alc1 recovery waiting period (see table 26 ) a period of recovery operation when any limiter operation does not occur during the alc1 operatio n. default is ? 00 ? (128/fs). alc1 recovery operation waiting period wtm1 wtm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 26 . alc1 recovery operation waiting period ztm1 - 0: zero crossing timeout for the write operation by the m p, alc1 recovery, and zero crossing enable (zelm bit = ? 0 ? ) of the alc1 operation. (see table 27 ) when the ipga of each l/r channels perform zero crossing or timeout independently, the ipga value is changed by the m p write operation, alc1 recovery operation or alc1 limiter operation (zelm bit = ? 0 ? ). default is ? 00 ? (128/fs). zero crossing timeout period ztm1 ztm0 8k hz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 27 . zero crossing timeout period rotm: period time for alc2 recovery operation 0 : 2048/fs (default) 1: 512/fs
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 53 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h alc mode control 1 0 alc2 alc1 zelm lmat1 lmat0 ratt lmth r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 0 0 0 lmth: alc1 limiter detection level / recovery waitin g counter reset level (see table 28 ) the alc1 limiter detection level and the alc1 recovery counter reset level may be offset by about 2db . default is ? 0 ? . lmth alc1 limiter detection level alc1 recovery waiting counter reset leve l 0 adc input 3 - 6.0dbfs - 6.0dbfs > adc input 3 - 8.0dbfs default 1 adc input 3 - 4.0dbfs - 4.0dbfs > adc input 3 - 6.0dbfs table 28 . alc1 limiter detection level / recovery waiting counter reset level ratt: alc1 recovery gain st ep (see table 29 ) during the alc1 recovery operation, the number of steps changed from the current ipga value is set. for example, when the current ipga value is 30h and ratt bit = ? 1 ? is set, the ipga changes to 32h by the alc1 rec overy operation and the output signal level is gained up by 1db (=0.5db x 2). when the ipga value exceeds the reference level (ref6 - 0 bits), the ipga value does not increase. ratt gain step 0 1 default 1 2 table 29 . alc1 recov ery gain step setting lmat1 - 0: alc1 limiter att step (see table 30 ) during the alc1 limiter operation, when either lch or rch exceeds the alc1 limiter detection level set by lmth, the number of steps attenuated from the current ip ga value is set. for example, when the current ipga value is 47h and the lmat1 - 0 bits = ? 11 ? , the ipga transition to 43h when the alc1 limiter operation starts, resulting in the input signal level being attenuated by 2db (=0.5db x 4). when the attenuation value exceeds ipga = ? 00 ? ( - 8db), it clips to ? 00 ? . lmat1 lmat0 att step 0 0 1 default 0 1 2 1 0 3 1 1 4 table 30 . alc1 limiter att step setting zelm: enable zero crossing detection at alc1 limiter operation 0: enable (default) 1: disable when the zelm bit = ? 0 ? , the ipga of each l/r channel perform a zero crossing or timeout independently and the ipga value is changed by the alc1 operation. the zero crossing timeout is the same as the alc1 recovery operation. when th e zelm bit = ? 1 ? , the ipga value is changed immediately .
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 54 - alc1: alc1 enable flag 0: alc1 disable (default) 1: alc1 enable alc1 is enabled when alc1 bit is ? 1 ? . default is ?0? (disable). alc2: alc2 enable flag 0: alc2 disable 1: alc2 enable (def ault) alc2 is enabled after initialization cycle(2048/fs=46.4ms@fs=44.1khz). this initialization cycle starts when pmspk bit is changed from ? 0 ? to ? 1 ? . default is ? 1 ? (enable). addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah alc mode control 2 0 ref6 ref 5 ref4 ref3 ref2 ref1 ref0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 1 1 0 1 1 0 ref6 - 0: reference value at a lc1 recovery operation (see table 31 ) during the alc1 recovery operation , if the ipga value exceeds the setting r eference value by gain operation, then the ipga does not become larger than the reference value. for example, when ref7 - 0 = ? 30h ? , ratt = 2step, ipga = 2fh, even if the input signal does not exceed the ? alc1 recovery waiting counter reset level ? , the ipga does n o t change to 2fh + 2step = 31h, and keeps 30h. default is ? 36h ? . gain (db) data (hex) mic input line input step 47 +27.5 +12.0 46 +27.0 +11.5 45 +26.5 +11.0 : : : 36 +19.0 +3.5 default : : : 2f +15.5 +0.0 : : : 10 + 0.0 - 15.5 : : : 06 - 5.0 - 20.5 05 - 5.5 - 21.0 04 - 6.0 - 21.5 03 - 6.5 - 22.0 02 - 7.0 - 22.5 01 - 7.5 - 23.0 00 - 8.0 - 23.5 0.5db table 31 . setting reference value at alc1 recovery operation
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 55 - addr register name d7 d6 d 5 d4 d3 d2 d1 d0 0bh lch input pga control 0 ipgal6 ipgal5 ipgal4 ipgal3 ipgal2 ipgal1 ipgal0 0fh rch input pga control 0 ipgar6 ipgar5 ipgar4 ipgar3 ipgar2 ipgar1 ipgar0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 ipgal6 - 0: lch inpu t analog pg a (see table 32 ) ipgar6 - 0: rch input analog pg a (see table 32 ) default: ? 10h ? (0db) when ipga gain is changed, ipgal6 - 0 and ipgar6 - 0 bits should be written while pmmicl, pmmicr, pm ipgl or pmipgr bit is ? 1 ? and alc1 bit is ? 0 ? . ipga gain is reset when pmmicl=pmmicr=pmipgl =pmipgr= ? 0 ? , and then ipga operation starts from the default value when pmmicl, pmmicr, pmipgl or pmipgr bit is changed to ? 1 ? . when alc1 bit is changed from ? 1 ? t o ? 0 ? , ipga holds the last gain value set by alc1 operation. when ipgal6 - 0 and ipgar6 - 0 bits are read, the register values written by the last write operation are read out regardless the actual gain. gain (db) data (hex) mic input line input step 47 +27.5 +12.0 46 +27.0 +11.5 45 +26.5 +11.0 : : : 36 +19.0 +3.5 : : : 2f +15.5 +0.0 : : : 10 +0.0 - 15.5 default : : : 06 - 5.0 - 20.5 05 - 5.5 - 21.0 04 - 6.0 - 21.5 03 - 6.5 - 22.0 02 - 7.0 - 22.5 01 - 7.5 - 23.0 00 - 8.0 - 23.5 0.5db table 32 . input gain setting addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch lch digital att control attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 0dh rch digital att control attr7 attr6 attr5 attr4 attr3 attr2 at tr1 attr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 attl/r7 - 0: digital att output control (see tab le 18 ) default: ? 00h ? (0db)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 56 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh volume control attm atts2 atts1 a tts0 0 0 0 0 r/w r/w r/w r/w r/w rd rd rd rd default 0 0 0 0 0 0 0 0 atts2 - 0: attenuator select of signal from ipga lch to stereo mixer. (see table 33 ) atts2 - 0 attenuation 7h - 6db 6h - 9db 5h - 12db defau lt 4h - 15db 3h - 18db 2h - 21db 1h - 24db 0h - 27db table 33 . attenuator table attm: attenuator control for signal from ipga lch to mono mixer 0: off. 0db (default) 1: on. ? 4db
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 57 - addr register name d7 d6 d5 d4 d3 d2 d1 d 0 10h power management 3 0 0 0 inr inl pmipgr pmmicr pmadr r/w rd rd rd r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmadr: adc rch block power control 0: power down (default) 1: power up when the pm ad l or pmadr bit changes from ?0? to ?1?, the in itializ ation cycle (2081/fs = 47.2ms @44.1khz) starts. after initializing , digital data of the adc is output. analog digital pmadl pmadr lch rch l/r 0 0 power down power down power down 0 1 power down power up power up 1 0 power up power down power up 1 1 power up power up power up table 34 . adc block power control pmmicr: mic power and ipga rch block power control 0: power down (default) 1: power up pmipgr: ipga rch block power control 0: power down (default) 1: power up ipga rch block is powered up if pmmicr or pmipgr bit is ? 1 ? (see table 35 ). pmmicr pmipgr mic - amp ipga 0 0 power down power down 0 1 power down power up 1 0 power up power up 1 1 power up power up table 35 . mic - amp and ipga rch block power control inl: ipga lch input select 0: mic input (lin1: default) 1: line input (lin2) inr: ipga rch input select 0: mic input (rin1: default) 1: line input (rin2)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 58 - system design figure 45 shows the system connection diagram for the AK4537. an evaluation board [akd4537] is available which demonstrates the optimum layout, power supply arrangements and measurement results. 0.1 m 10 m 0.1 m 10 m analog supply 2.4 ~ 3.6v 0.1 m 10 m 2.2 m 0.1 m 0.1 m 10 m analog supply 2.4 ~ 3.6v micout l 1 2 3 4 5 6 7 8 9 10 11 12 13 micout r ext /mcr mpe mpi int / micl vcom avss avdd pvdd pvss vcoc nc rin1 52 51 50 49 lin1 beepl beepr 48 47 45 44 46 42 41 43 40 beepm lin2 rin2 mout+ mout- lout rout mout2 min 39 38 37 36 35 34 33 32 31 30 29 28 27 mutet hpl hpr hvss hvdd spn spp m/s xti/mcki xto dvss dvdd cad0 14 pdn 15 16 csn/cad1 17 cclk/scl 18 cdti/sda 19 cdto 20 i2c 21 sdti 22 sdto 23 lrck 24 bick 25 mcko 26 reset dsp and up top view r r r 1 m 8 w 10k w 4.7n 10 1 m 2.2k 1 m 2.2k 1 m 1 m 1 m 1 m 1 m nc nc c c c c 1 m r 1 m c r c 1 m 16 w 16 w 6.8 w 6.8 w 47 m 10 w 0.22 m 10 w 0.22 m not es: - avss, dvss, pvss and hvss of the AK4537 should be distributed separately from the ground of external controllers. - values of r and c in figure 45 should depend on system. - all input pins should not be left floating. figure 45 . typical connection diagram
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 59 - 1. grounding and power supply decoupling the AK4537 requires careful attention to power supply and grounding arrangements. avdd, dvdd, pvdd and hvdd are usually supplied from the system ? s analog supply. if avdd, dvdd, pvdd and hvdd are supplied separately, the correct power up sequence should be observed . avss, dvss, pvss and hvss of the AK4537 should be connected to the analog ground plane. system analog ground and digital gro und should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK4537 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 m f electrolytic capacitor in parallel with a 0.1 m f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clo cks, should be kept away from the vcom pin in order to avoid unwanted coupling into the AK4537. 3. analog inputs the mic, line and beep inputs are single - ended. the input signal range scales with nominally at 0.06 x avdd vpp for the mic input and 0.6 x a vdd vpp for the beep input, centered around the internal common voltage (0.45 x avdd). usually the input signal is ac coupled using a capacitor. the cut - off frequency is fc = (1/2 p rc). the AK4537 can accept input voltages from avss to avdd. 4. analog outp uts the input data format for the dac is 2 ? s complement. the output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). mono output from the mout2 pin and mono line output from the mout+ and mout - pins are cente red at 0.45 x avdd. the headphone - amp and speaker - amp outputs are centered at hvdd/2.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 60 - contorol sequence n power up upon power - up, bring the pdn pin = ?l?. initialize the internal registers to default value s after the pdn pin = ?h?. set the following registers to establish the initial condition. power supply pdn pin pmvcm bit (addr:00h, d7) dif1-0 bits (addr:04h, d1-0) bf bit (addr:04h, d2) pll1-0 bits (addr:04h, d7-6) mout2 bit (addr:02h, d0) alcs bit (addr:02h, d1) dahs bit (addr:03h, d7) (2) 10 xx x xx 00 0 (3) (4) (6) (5) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz (1) power supply (2) pdn pin = ? l ? ? ? h ? (3) addr:00h, data 80h (4) addr:02h, data 03h (5) addr:03h, data 83h (6) addr:04h, data 42h figure 46 . power up sequence (1) power supply (2) pdn pin = ? l ? ? ? h ? ? l ? time of 150ns or more is needed to reset the a k4537. (3) power up vcom : pmvcm bit = ? 0 ? ? ? 1 ? vcom should first be powered up before the other block operates. (4) set up register 02h : mout2 bit = alcs bit = ? 0 ? ? ? 1 ? set the mout2 and alcs bits to ? 1 ? when using the speaker - amp. (5) set up register 03h : hpl b it = hpr bit = ? 1 ? ? ? 0 ? , dahs bit = ? 0 ? ? ? 1 ? (6) set up register 04h dif1 - 0 bits set the audio interface format. bf bit sets bick output frequency in master mode. pll1 - 0 bits set mclk input frequency in pll mode.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 61 - n clock set up when adc, dac, alc1 a nd alc2 are used, the clocks (mclk, bick and lrck) must be supplied. 1. when x'tal is used in pll mode. (slave mode) mckpd bit (addr:01h, d7) bick, lrck (slave mode) ps1-0 bits (addr:04h, d5-4) pmxtl bit (addr:01h, d6) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 40ms(max) output input (1) 20ms(typ) (2) (3) (4) (5) (6) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:40h (2) addr:01h, data:60h (3) addr:04h, data 4ah (4) mcko output starts (5) bick and lrck input start (6) addr:04h, data 6ah figure 47 . clock set up sequence (1) (1) release th e pull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? and power - up the x ? tal oscillator: pmxtl bit = ? 0 ? ? ? 1 ? (2) power - up the pll : pmpll bit = ? 0 ? ? ? 1 ? the pll should be powered - up after the x ? tal oscillator becomes stable. it takes x ? tal oscillator 20ms(typ) to be stable after pmxtl bit= ? 1 ? . this time depends on x ? tal. pll needs 40ms lock time the pmpll bit = ? 0 ? ? ? 1 ? . (3) enable mcko output : mcko bit = ? 0 ? ? ? 1 ? (4) mcko is output after pll becomes stable. (5) input bick and lrck synchronized with the mcko output. (6) se t the mcko output frequency (ps1 - 0 bits) if ps1 - 0 bits are changed before lrck is input, mcko is not output. ps1 - 0 bits should be changed after lrck is input.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 62 - 2. when x'tal is used in pll mode. (master mode) mckpd bit (addr:01h, d7) bick, lrck (master mode) ps1-0 bits (addr:04h, d5-4) pmxtl bit (addr:01h, d6) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 40msec(max) output output (1) 20ms(typ) (2) (3) (4) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:40h (2) addr:01h, data:60h (3) addr:04h, data 6ah (4) mcko, bick and lrck output starts figure 48 . clock set up sequence (2) (1) release the pull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? and and power - up the x ? tal oscillator: pmxtl bit = ? 0 ? ? ? 1 ? (2) power - up pll : pmpll bit = ? 0 ? ? ? 1 ? the pll shoul d be powered - up after the x ? tal oscillator becomes stable. it takes x ? tal oscillator 20ms(typ) to be stable after pmxtl bit= ? 1 ? . this time depends on x ? tal. pll needs 40ms lock time the pmpll bit = ? 0 ? ? ? 1 ? . (3) enable mcko output : mcko bit = ? 0 ? ? ? 1 ? and s et up mcko output frequency (ps1 - 0 bits) (4) mcko, bick and lrck are output after pll lock time.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 63 - 3. when an external clock is used in pll mode. (slave mode) mckpd bit (addr:01h, d7) ps1-0 bits (addr:04h, d5-4) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 (1) output bick, lrck (slave mode) input external mclk input (2) (3) 40ms(max) (4) (5) (6) (7) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:00h (2) input external mclk (3) addr:01h, data 2 0h (5) mcko output starts (6) bick and lrck input start (7) addr:04h, data 6ah (4) addr:04h, data 4ah figure 49 . clock set up sequence (3) (1) release the pull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? (2) input an external mclk (3) power - up pll : pmpll bit = ? 0 ? ? ? 1 ? pll needs 40ms lock time after the pmpll bit = ? 0 ? ? ? 1 ? . (4) enable mcko output : mcko bit = ? 0 ? ? ? 1 ? (5) mcko is output after pll lock time. (6) input bick and lrck that synchronized in the mcko output. (7) set up mcko output frequency (ps1 - 0 bits) if ps1 - 0 bits are changed before lrck is input, mcko is not output. ps1 - 0 bits should be changed after lrck is input.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 64 - 4. when an external clock is used in pll mode. (master mode) mckpd bit (addr:01h, d7) ps1-0 bits (addr:04h, d5-4) pmpll bit (addr:01h, d5) mcko bit (addr:04h, d3) mcko pin xx 00 40ms(max) output bick, lrck (master mode) output external mclk input (1) (2) (3) (4) (5) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:01h, data:00h (2) input external mclk (3) addr:01h, data 20h (5) mcko, bick and lrck output starts (4) addr:04h, data 6ah figure 50 . clock set up sequence (4) (1) release the pull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? (2) input an ex ternal mclk (3) power - up pll : pmpll bit = ? 0 ? ? ? 1 ? pll needs 40ms lock time after the pmpll bit = ? 0 ? ? ? 1 ? . (4) enable mcko output : mcko bit = ? 0 ? ? ? 1 ? and set up mcko output frequency (ps1 - 0 bits) (5) mcko, bick and lrck are output after pll lock time. 5. externa l clock mode mckpd bit (addr:01h, d7) fs1-0 bits (addr:05h, d6-5) xx 00 bick, lrck (slave mode) input external mclk input bick, lrck (master mode) output (1) (2) (3) (4) (5) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock frequency : 256fs output master clock frequency : 64fs (1) addr:01h, data:00h (2) addr:05h, data 00h (3) input external mclk (4) input bick and lrck(slave) (5) bick and lrck output(master) figure 51 . clock set up sequence (5) (1) release the pull - down of the xti pin : mckpd bit = ? 1 ? ? ? 0 ? (2) set up mclk frequency (fs1 - 0 bits) (3) input an external mclk (4) in slave mode, input mclk, bick and lrck. (5) in master mode, while mclk is input, bick and lrck are output.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 65 - n mic input recording (mono) fs2-0 bits (addr:05h, d7-5) mic control (addr:07h, d2-0) pmadl bit (addr:00h, d0) pmmicl bit (addr:00h, d1) adc internal state xxx 000 00001 xx1xx power down initialize normal state power down 2081 / fs (1) (2) (6) (7) alc1 state alc1 enable alc1 disable alc1 disable (5) alc1 control 1 (addr:08h) xxh 00h (3) alc1 control 2 (addr:0ah) xxh 47h (4) alc1 control 3 (addr:09h) xxh 61h or 21h example : x ? tal and pll are used. sampling frequency : 8khz mic select : internal mic pre mic amp : +20db mic power on alc1 setting : refer to figure 9 alc2 bit = ? 1 ? (default) (1 ) addr:05h, data:e0h (3) addr:08h, data:00h (4) addr:0ah, data:47h (5) addr:09h, data:61h (2) addr:07h, data:0dh ( 6) addr:00h, data 83h recording (7) addr:00h, data 80h figure 52 . mic input recordin g sequence this sequence is an example of alc1 setting at fs=8khz. if the parameter of the alc1 is changed, please refer to ? figure 22 . registers se t - up sequence at alc1 operation ? at first, clocks shou ld be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs2 - 0 bits). when the ak4536 is pll mode, mic and adc should be powered - up in consideration of pll lock time after a sampling frequency is changed. (2) set up mic input (addr: 07 h) (3) set up timer select for alc1 (addr: 08h) (4) set up ref value for alc1 (addr: 0ah) (5) set up lmth, ratt, lmat1 - 0, alc1 bits (addr: 09h) (6) power up mic and adc: pmmicl bit = pmadl bit = ? 0 ? ? ? 1 ? (in case of stereo mic, pmmicr and pmadr bits also should be set to ? 1 ? . ) the initialization cycle time of adc is 2081/fs=47.2ms@fs=44.1khz. after the alc1 bit is set to ? 1 ? and mic block is powered - up, the alc1 operation starts from ipga initial value (0db). (7) power down mic and adc: pmmic bit = pmadc bit = ? 1 ? ? ? 0 ? (in c ase of stereo mic, pmmicr and pmadr bits also should be set to ? 0 ? . ) when the registers for the alc1 operation are not changed, alc1 bit may be keeping ? 1 ?. the alc1 operation is disable d because the mic block is powered - down. if the registers for the alc1 operation are also changed when the sampling frequency is changed, it should be done after the AK4537 goes to the manual mode (alc1 bit = ? 0 ? ) or mic block is powered - down (pmmicl bit = ? 0 ? ). ipga gain is reset when pmmicl =pmmicr=pmipgl=pmipgr= ? 0 ? , and then ipga operation starts from the default value when pmmicl, pmmicr, pmipgl or pmipgr bit is changed to ? 1 ? .
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 66 - n headphone - amp output fs2-0 bits (addr:05h, d7-5) attl7-0 bits (addr:0ch 0dh, d7-0) hpl/r bit (addr:03h, d1-0) pmhpl/r bits (addr:01h, d2-1) hpl/r pins xxx 000 0000000 xxxxxxx normal output external mute (1) bst1-0 bits (addr:06h, d3-2) 00 xx 00 (2) (3) (7) (8) (12) pmdac bit (addr:01h, d0) (4) (11) (5) (9) (6) (10) example : x ? tal and pll are used. sampling frequency : 44.1khz dattc bit = ? 1 ? (default) digital attenuator level : - 8db bass boost level : middle de - emphases response : off soft mute time : 1024/fs (1) addr:05h, data:00h (3) addr:0ch, data 10h (4) addr:01h, data 61h (7) release external mute playb ack (2) addr:06h, data 19h (8) enable external mute (9) addr:01h, data 61h (10) addr:02h, data 83h (5) addr:02h, data 80h (6) addr:01h, data 67h (11) addr:01h, data 60h (12) addr:06h , data 11h figure 53 . headphone - amp output sequ ence at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs2 - 0 bits) if pll mode is used. (2) set up the low frequency boost level(bst1 - 0 bits) (3) set up the digital volume(addr : 0ch and 0dh) at datt c bit = ? 1 ? (default), attl7 - 0 bits of address 0ch control both lch and rch attenuation level. (4) power up dac : pmdac bit = ? 0 ? ? ? 1 ? (5) power up headphone - amp : hpl bit = hpr bit = ? 1 ? ? ? 0 ? output voltage of headphone - amp is still hvss. (6) rise up the common volt age of headphone - amp : pmhpl bit = pmhpr bit = ? 0 ? ? ? 1 ? the rising time after power up headphone - amp depends on the capacitor value connected with the mutet pin. when this capacitor value is 1.0 m f, the time constant is t r = 100ms. (7) release the external mut e. (8) enable the external mute. (9) fall down the common voltage of headphone - amp : pmhpl bit = pmhpr bit = ? 1 ? ? ? 0 ? the rising time after power up headphone - amp depends on the capacitor value connected with the mutet pin. when this capacitor value is 1.0 m f, the time constant is t f = 100ms. if the power supply is powered off or headphone - amp is powered - down before the common voltage goes to gnd, some pop noise occurs. it takes 2times of t f that the common voltage goes to gnd. (10) power down headphone - amp : hpl bit = hpr bit = ? 0 ? ? ? 1 ? (11) power down dac : pmdac bit = ? 1 ? ? ? 0 ? (12) off the low frequency boost level (bst1 - 0 bits = ? 00 ? )
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 67 - n speaker - amp output fs2-0 bits (addr:05h, d7-5) attl7-0 bits (addr:0ch 0dh, d7-0) pmdac bit (addr:01h, d0) pmspk bit (addr:01h, d3) xxx 000 0000000 xxxxxxx spp pin normal output spps bit (addr:05h, d0) hi-z hi-z spn pin normal output hi-z hi-z hvdd/2 hvdd/2 (1) (3) x 0 (2) alc2 bit (addr:09h, d6 (4) (5) (7) (6) example : x ? tal and pll are used. sampling frequency : 48khz dattc bit = ? 1 ? (default) digital attenuator level : 0db alc1 : disable alc2 : disable (1) addr:05h, data60h (3) addr:0ch, data 00h (4) addr:01h, data 69h (5) addr:05h, data 61h playback (2) addr:09h, data 00h (6) addr:05h, data 60h (7) add r:01h, data 60h figure 54 . speaker - amp output sequen ce at first, clocks should be supplied according to ? clock set up ? sequence. (1) set up a sampling frequency (fs2 - 0 bits) if pll mode is used. (2) set up the alc2 enable/disable(alc2 bit) (3) set up the digital volume(addr : 0ch and 0dh) at dattc bit = ? 1 ? (default), attl7 - 0 bits of address 0ch control both lch and rch attenuation level. (4) power up of dac and speaker - amp : pmdac bit = pmspk bit = ? 0 ? ? ? 1 ? the initializing time of speaker - amp is 2048/fs=46.4ms@fs=44.1khz. (5) exit the power - save - mode of speaker - am p : spps bit = ? 0 ? ? ? 1 ? (6) enter the power - save - mode of speaker - amp : spps bit = ? 1 ? ? ? 0 ? (7) power down dac and speaker - amp : pmdac bit = pmspk bit = ? 1 ? ? ? 0 ?
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 68 - n stop of clock mclk can be stopped when pmmic=pmadc=pmdac=pmspk= ? 0 ? . 1. when x ? tal is used in pll mode mckpd bit (addr:01h, d7) pmxtl bit (addr:01h, d6) pmpll bit (addr:01h, d5) mcko bit (addr:03h, d4) (1) (2) example : audio i/f format : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:04h, data:62h (2) addr:01h, data:80h figure 55 . stop of clock sequence (1) (1) disable mcko output : mcko bit = ? 1 ? ? ? 0 ? (2) power down x ? tal and pll, pull down the xti pin : pmxtl bit = pmpll bit = ? 1 ? ? ? 0 ? , mckpd = ? 0 ? ? ? 1 ? 2. when an external clock is used in pll mode mckpd bit (addr:01h, d7) external mclk pmpll bit (addr:01h, d5) mcko bit (addr:03h, d4) input (1) (2) (3) example : audio i/f : i 2 s bick frequency at master mode : 64fs input master clock select at pll mode : 11.2896mhz output master clock frequency : 64fs (1) addr:04h, data:62h (2) addr:01h, data:80h (3) stop external clock figure 56 . stop of clock sequence (2) (1) stop mcko output : mcko bit = ? 1 ? ? ? 0 ? (2) power down pll, pull down the xti pin : pmpll bit = ? 1 ? ? ? 0 ? , mckpd = ? 0 ? ? ? 1 ? when the external mclk becomes hi - z or the external mclk is input by ac couple, mcki pin should be pulled down. (3) stop an external mclk
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 69 - 3. external clock mode mckpd bit (addr:01h, d7) external mclk input example : (1) addr:01h, data:80h (2) stop external clock figure 57 . stop of clock sequence (3) (1) pull down the xti pin : mckpd = ? 0 ? ? ? 1 ? when the external mclk becomes hi - z or the external mclk is input by ac couple, mcki pin should be pulled down. (2) stop an external mclk n power down power down vcom(pmvcm= ? 1 ? ? ? 0 ? ) after all blocks except vcom are powered down and mclk stops. the AK4537 is also powered - down by pdn pin = ? l ? . when pdn pin = ? l ? , the registers are initialized.
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 70 - package 52pin qfn (unit: mm) 7.2 0.20 14 26 7.2 0.20 0.30 0.10 7.0 0.10 7.0 0.10 0.21 0.05 0.60 + 0.10 - 0.30 0.05 0.02 + 0.03 - 0.02 0.78 + 0.17 - 0.28 0.80 + 0.20 - 0.00 13 1 52 40 27 39 27 39 40 52 13 1 14 26 0.20 + 0.10 - 0.20 45 45 0.05 m 4 - c0.6 0.18 0.05 0.40 note) the part of black at four corners on reverse side must not be soldered and must be open. n material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate (pb free)
asahi kasei [ AK4537] ms0202 - e - 02 2003/5 - 71 - marking 1 AK4537vn xxxxxxx akm xxxxxxx : date code identifier (7 digits) i m portant notice these products and their specifications are subject to change without notice. before considering any use or application, con sult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any info rmation contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exc hange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distribut or of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liabilit y for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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